1. Field of the Invention
The present invention relates to a semiconductor device manufacturing method.
2. Description of the Related Art
Recently, an increase in demand for an environmentally friendly automobile and a consumer electrical appliance lead to a growing demand for power saving of a power switching device. In a breakdown voltage class of 1000V or less, a most mainstream switching device is a power MOSFET (Metal Oxide Semiconductor Field Effect Transistor: an insulated gate field effect transistor) suitable for fast switching. The device structure (element structure) of a power MOSFET is divided broadly into a vertical type and a horizontal type, and a vertical type power MOSFET has characteristics superior to a horizontal type power MOSFET in terms of a large current and low on-resistance.
In order to achieve power saving in the vertical type power MOSFET, researches on a reduction in on-resistance exceeding the physical property limit of a silicon (Si) semiconductor have been promoted. As a MOSFET responding to the demand for power saving, a semiconductor device having a charge compensation device structure which compensates for the charge amount in a drift layer, which is a current path, is known. As a typical device structure of the charge compensation type, a super junction (SJ) structure with a drift layer as a parallel pn layer wherein n-type regions and p-type regions are alternately disposed in a direction parallel to a main surface of a substrate (hereafter referred so as a lateral direction) is known.
In a heretofore known MOSFET with a drift layer configured of only single conductivity type regions, when applying a voltage between the source and the drain, a depletion layer extends from a pn junction between a base region and the drift layer in a direction perpendicular to the main surface of the substrate (a substrate depth direction (hereafter referred to as a vertical direction)). Therefore, the electric field strength in the drift layer decreases toward the rear surface of the substrate. Meanwhile, in a MOSFET of a super junction structure (hereafter referred to as a super junction MOSFET), when applying a voltage between the source and the drain, a depletion layer extends in the lateral direction from the pn junctions between the n-type regions and p-type regions of the parallel pn layer configuring the drift layer. Therefore, in an ideal super junction MOSFET, the electric field strength in the drift layer is uniform regardless of a depth position.
Consequently, in the super junction MOSFET, when the impurity concentration distribution of the drift layer is set to the same level as in the heretofore known MOSFT, breakdown voltage characteristics calculated with the value of an integral of the electric field strength are superior to those of the heretofore known MOSFET even though the maximum electric field strength and on-resistance are at the same level as in the heretofore known MOSFET. The application of a super junction semiconductor device having these kinds of characteristics is spreading even to the field using a power device of a low breakdown voltage class. However, the need for a miniaturization (a reduction in the repetitive pitch of the n-type regions and p-type regions of the parallel pn layer), as well as for an increase in the impurity concentration of the n-type regions and p-type regions of the parallel pn layer, in order to reconcile both a low on-resistance and a reduction in turn-on characteristics, poses an impediment to the application of the super junction structure to a low breakdown voltage power device.
Also, in the power device, the maintenance of the breakdown voltage of a termination structure portion poses a challengem. Therefore, structural measures to increase the breakdown voltage are also necessary for the super junction semiconductor device. As a super junction semiconductor device with the increased breakdown voltage, a device wherein the parallel pn layer configuring the drift layer is disposed from an active region over to the termination structure portion is proposed. It is a useful method to reduce the repetitive pitch of the n-type regions and p-type regions of the parallel pn layer in the termination structure portion. Also, from the viewpoint of securing the breakdown voltage, it is preferable, in order to expand the range in which a depletion layer extends, that the n-type regions and p-type regions of the parallel pn layer are disposed so that the parallel pn layer extends to a surface of a semiconductor portion (the interface between the front surface of the substrate and an interlayer insulating film) in the termination structure portion.
It is possible to form the upper end portions (the surface side portions of the semiconductor portion) of the p-type regions of the parallel pn layer, at the same time as a p-type RESURF region, by ion implantation for forming a p-type region (hereafter referred to as a p-type RESURF region) configuring a known RESURF (REduced SURface Field) structure. That is, when forming an ion implantation mask for forming the p-type RESURF region, portions of the ion implantation mask above the p-type regions of the parallel pn layer are also opened, and p-type impurity ion implantation is carried out using the ion implantation mask. Specifically, the parallel pn layer is formed in the following way.
FIG. 24 is a sectional view showing a condition of a heretofore known super junction semiconductor device in the process of being manufactured. As shown in FIG. 24, firstly, an n-type epitaxial layer 102 is deposited on the front surface of an n+-type semiconductor substrate 101 by an epitaxial growth method. Next, n-type impurity regions 121 forming n-type regions of a parallel pn layer is formed in the surface layer of the n-type epitaxial layer 102 by photolithography and n-type impurity ion implantation (the dot-shaded portions). Next, p-type impurity regions 122 forming p-type regions of the parallel pn layer are formed in the surface layer of the n-type epitaxial layer 102 by photolithography and p-type impurity ion implantation (the diagonally hatched portions). That is, the n-type impurity regions 121 and the p-type impurity regions 122 are alternately formed in the n-type epitaxial layer 102.
Next, an n-type epitaxial layer (hereafter referred to as an upper n-type epitaxial layer 102) is further deposited on the n-type epitaxial layer 102 (hereafter referred to as the lower n-type epitaxial layer 102) by an epitaxial growth method. Next, n-type impurity regions 121 and p-type impurity regions 122 are formed in the surface layer of the newly deposited upper n-type epitaxial layer 102 so as to be opposed in the vertical direction to the respective n-type impurity regions 121 and p-type impurity regions 122 of the lower n-type epitaxial layer 102. The deposition of the epitaxial layers 102 and the formation of the n-type impurity regions 121 and p-type impurity regions 122 are repeatedly carried out in this way, thus increasing the thickness of the n-type epitaxial layer 102.
Next, an uppermost n-type epitaxial layer 102 is further deposited on the n-type epitaxial layer 102. Next, a resist mask 131 acting as an ion implantation mask for forming the p-type RESURF region (not shown) is formed on the uppermost n-type epitaxial layer 102 by photolithography and etching. Opening portions are formed in portions of the resist mask 131 corresponding to regions in which to form the p-type RESURF region and in portions thereof above the p-type impurity regions 122 of the lower layer. Next, p-type impurity ion implantation 132 is carried out with the resist mask 131 as a mask, thus forming the p-type RESURF region and p-type impurity regions 122 (the p-type impurity regions 122 are not shown) in the surface layer of the uppermost n-type epitaxial layer 102.
Portions on which no n-type impurity ion implantation for forming the n-type impurity regions 121 is carried out, and into which no p-type impurity is introduced (that is, portions covered by the resist mask 131), are left as the n-type regions in the uppermost n-type epitaxial layer 102. Subsequently, the vertically opposed n-type impurity regions 121, and the vertically opposed p-type impurity regions 122, of the individual n-type epitaxial layers 102 deposited on the n+-type semiconductor substrate 101 are connected together, at the same time as the p-type RESURF region being diffused, by thermal diffusion treatment (drive-in) for diffusing the p-type RESURF region. By so doing, the parallel pn layer (not shown) is formed so as to extend to the surface of the semiconductor portion, thus completing the step of forming the parallel pn layer.
It is known that when a thick insulating film such as a LOCOS (Local Oxidation of Silicon: local insulating) film 106 is provided on the front surface of the substrate in the termination structure portion, an electric field concentrates on a portion below a level difference (a portion of the semiconductor portion in contact with an end portion 107 of the LOCOS film 106) formed on the surface of the semiconductor portion by a thickness-reduced end portion (the LOCOS bird's beak) 107 of the LOCOS film 106, thus causing a breakdown. Therefore, the measures to avoid the electric field concentration occurring immediately below (below the level difference of) the end portion 107 of the LOCOS film 106 are taken. The LOCOS bird's beak is a portion of the LOCOS film 106 formed with a silicon nitride film as a mask, which has grown so as to get under the mask, and is the beak of the bird shaped end portion 107, the thickness of which decreases toward the outside.
As a method of avoiding the electric field concentration occurring immediately below the end portion of the LOCOS film in the termination structure portion, a method whereby first and second concentration regions different in impurity concentration are formed immediately below the LOCOS film (in a portion of the semiconductor portion in contact with the LOCOS film) by carrying out p-type impurity ion implantation after forming a nitride film for forming the LOCOS film, and subsequently forming the LOCOS film, in a semiconductor device of a configuration wherein no parallel pn layer is provided in the termination structure portion, is proposed (for example, refer to JP-A-2009-016618 (paragraphs 0035 to 0041 and FIGS. 6 and 7)). In JP-A-2009-016618, the electric field concentration immediately below the end portion of the LOCOS film is relaxed by making the impurity concentration of the active region side first concentration region higher than that of the end portion of the LOCOS film and making the impurity concentration of the outside (chip end portion side) second concentration region higher than that of the first concentration region.
Also, as another method, a method whereby a RESURF region is formed, on the parallel pn layer of the termination structure portion, to a wide width so as to be disposed below a level difference, formed by a thickness-reduced end portion of a field insulating film, and so as to cover adjacent n-type regions and p-type regions of the parallel pn layer, is proposed (for example, refer to JP-A-2009-105110 (paragraph 0016)). In JP-A-2009-105110, as the RESURF region is formed to a wide width so as to cover a plurality of p-type regions of the parallel pn layer, it is possible to easily form the RESURF region immediately below the end portion of the field insulating film even when applied to the method of forming the parallel pn layer by repeatedly carrying out the deposition of the epitaxial layer and the ion implantation for forming the n-type regions and p-type regions forming the parallel pn layer in the deposited epitaxial layer, as heretofore described.
Also, as another method, the following method is proposed. Firstly, a p−-type RESURF region is formed in the surface layer of an n−-type semiconductor layer, and after a trench is formed, a gate insulating film is formed along the inner wall of the trench, and a thick oxide film is formed on the front surface of the substrate. Next, a gate electrode is formed in the trench via the gate insulating film, and gate polysilicon wiring is formed on the thick oxide film. Subsequently, p-type impurity ion implantation is carried out with the gate polysilicon wiring as a mask, and a p-type well region is formed on the active region side of the p−-type RESURF region so as to overlap with the p−-type RESURF region (for example, refer to JP-A-2009-105268 (paragraph 0014)). In JP-A-2009-105268, it is possible to form the p-type well region from immediately below the thick oxide film or immediately below the end portion of the thick oxide film over to the active region side.
Also, as another method, a method whereby after a plurality of trenches are formed in the n−-type semiconductor layer in the termination structure portion, the parallel pn layer is formed by epitaxially growing a p-type buried layer in the trenches, on each occasion of which a relay diffusion region is formed in the surface layer of the p-type buried layer by p-type impurity ion implantation, and an insulating film is formed on the front surface of the substrate in the termination structure portion by a chemical vapor deposition (CVD) method so as to cover the relay diffusion region, is proposed (for example, refer to JP-A-2013-102087 (paragraphs 0038 to 0042 and FIGS. 2 and 3)). In JP-A-2013-102087, as the LOCOS oxidation accounting for a significant proportion of the heat history of the semiconductor portion in process of manufacture is not carried out, it is possible to avoid an occurrence of an excess impurity diffusion.
However, in JP-A-2009-105110 and JP-A-2009-105268, when the width of the opening portions of the ion implantation mask for forming the parallel pn layer is narrow, it is not possible to carry out p-type impurity ion implantation in a normal way. The reason is as follows. In the low breakdown voltage power device, as it is necessary to miniaturize the n-type regions and p-type regions of the parallel pn layer, as heretofore described, a microscopic opening pattern is formed in the ion implantation mask for forming the parallel pn layer. In this case, it is not possible to carry out the patterning of the ion implantation mask as designed depending on the height of a level difference formed on a surface of an element, or on the distance between the level difference and the mask opening portions. Therefore, when forming the p-type regions in the surface layer of the parallel pn layer and the p-type region immediately below the end portion of the insulating film using ion implantation and thermal diffusion treatment, it is not possible to accurately form the p-type regions in the vicinity of the level difference of the surface of the element.
For example, the carrier distribution of the parallel pn layer of the super junction semiconductor device fabricated (manufactured) in accordance with the heretofore known method heretofore described (refer to FIG. 24) is observed with a scanning capacitance microscopy (SCM). FIG. 25 is a sectional view schematically showing a condition in which a defect is caused in the process of manufacturing the heretofore known super junction semiconductor device. A design width w1 of the opening portions of the resist mask 131 for forming the p-type regions 112 in the uppermost n-type epitaxial layer 102, of the plurality of n-type epitaxial layers 102 deposited on the n+-type semiconductor substrate 101, is set to 0.40 μm. After carrying out the p-type impurity ion implantation 132 for forming the p-type regions 112 using the resist mask 131, the n-type impurity regions 121 and p-type impurity regions 122 of the individual n-type epitaxial layers 102 stacked on the n+-type semiconductor substrate 101 are diffused by thermal diffusion treatment.
As a result of this, it is confirmed, as shown in FIG. 25, that in the individual n-type epitaxial layers 102 other than the uppermost layer, the vertically opposed n-type impurity regions 121 connect together, and the vertically opposed p-type impurity regions 122 connect together, thus forming n-type regions 113 and p-type regions 111 of a parallel pn layer 103. It is confirmed that the p-type regions 112 are formed in portions of the uppermost n-type epitaxial layer 102 apart from the end portion 107 of the LOCOS film 106 so as to connect with the p-type regions 111 of the parallel pn layer 103. However, it is confirmed that the p-type regions 112 are not formed in a vicinity 133 of the end portion of the LOCOS film 106 in the uppermost n-type epitaxial layer 102, and that an n-type region 114b is left in a portion on the p-type regions 111 of the parallel pn layer 103 so as to connect regions 114a which are left in a portion on the n-type regions 113 of the parallel pn layer 103 by being covered with the resist mask 131.
That is, it is confirmed that a pattern defect of the resist mask 131 occurs, and the p-type impurity ion implantation 132 is not carried out in a normal way, in the vicinity 133 of the end portion of the LOCOS film 106. The reason is as follows. A level difference (an unevenness) formed by the LOCOS film 106 occurs on the surface of the semiconductor portion in the vicinity 133 of the end portion of the LOCOS film 106 by the time before forming the resist mask 131. When the resist mask 131 having microscopic opening portions is formed on the level difference of the surface of the semiconductor portion, the allowable limit of the patterning accuracy of the resist mask 131 is exceeded, thus inducing a pattern defect such as no formation of the opening portions of the resist mask 131. This reduces the accuracy of p-type impurity ion implantation. It is confirmed by the present inventors that the breakdown voltage of the termination structure portion is significantly reduced by the level difference of the surface of the semiconductor portion formed by the LOCOS film 106 being positioned on the n-type region 114b surface which increases in current density.
Also, when using a microscopically patterned ion implantation mask, it is difficult to form p-type regions in a predetermined shape and predetermined positions not only when forming the p-type regions 112 exposed to the surface of the semiconductor portion in order to extend the parallel pn layer 103 to the surface of the semiconductor portion, but also when forming an element structure including p-type regions formed so as to be exposed to the surface of the semiconductor portion. Therefore, there is a concern about an adverse effect on element characteristics due to a pattern defect of the ion implantation mask. In JP-A-2009-016618, as p-type impurity ion implantation is carried out on predetermined positions in a condition in which no level difference is formed on the surface of the semiconductor portion, the heretofore described problem raised by the level difference of the surface of the semiconductor portion is solved. However, when including a field plate-like structure as in a low breakdown voltage power device including a microscopic super junction structure, it is eventually difficult to form a predetermined element structure. The reason is as follows.
For example, when carrying out heat treatment, such as in the formation of the LOCOS film 106, after p-type impurity ion implantation, the diffusion of the p-type impurity regions 122 increases by a heat history such as that of the formation of the LOCOS film 106 being added. Therefore, there is a possibility that the p-type regions 111 (p-type impurity regions 122) connect together in the lateral direction and the n-type regions 113 (n-type impurity regions 121) of the parallel pn layer disappear. Particularly, when ion implanting no n-type impurity when forming the p-type regions 112 and n-type regions 114a in the uppermost n-type epitaxial layer 102 in order to extend the parallel pn layer 103 to the surface of the semiconductor portion, the p-type regions 112 are compensated with p-type impurities, while the n-type regions 114a are not compensated with n-type impurities. Therefore, there is a concern that the n-type regions 114a adjacent to the p-type regions 112 disappear due to a lateral diffusion of the p-type regions 112, and the p-type regions 112 connect together in the lateral direction, in the uppermost n-type epitaxial layer 102.
Also, not only in the n-type regions 114a and p-type regions 112 formed in the uppermost n-type epitaxial layer 102, but also in the n-type regions 113 and p-type regions 111 formed in the lower n-type epitaxial layer 102, an excess impurity diffusion accelerates the compensation of the n-type regions 113 with p-type impurities and the compensation of the p-type regions 111 with n-type impurities. Therefore, to carry out heat treatment, such as in the formation of the LOCOS film, after the n-type impurity and p-type impurity ion implantation for forming the parallel pn layer 103 causes a deterioration in on-resistance. In JP-A-2013-102087, as an insulating film is formed by the CVD method in place of the LOCOS film, it is possible to avoid the heat history experienced by the formation of the LOCOS film involving the semiconductor portion, but there is the problem that the insulating film formed by the CVD method is inferior in insulation properties and coating properties to the LOCOS film.
In order to solve the heretofore described challenges raised by the heretofore known technologies, the invention has for its object to provide a semiconductor device manufacturing method whereby it is possible to improve element characteristics and it is possible to accurately form a super junction structure.